Invention Grant
- Patent Title: Semiconductor integrated device and method of testing semiconductor integrated device
- Patent Title (中): 半导体集成器件及半导体集成器件测试方法
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Application No.: US12369699Application Date: 2009-02-11
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Publication No.: US08386804B2Publication Date: 2013-02-26
- Inventor: Fumio Yoshiya
- Applicant: Fumio Yoshiya
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2008-140037 20080528
- Main IPC: G06F11/30
- IPC: G06F11/30 ; G06F7/02

Abstract:
According to one embodiment, a semiconductor integrated device which stores secret data and is capable of operating in a test mode in which a scan test with respect to an internal circuit is executed, the semiconductor integrated device comprises a mode signal receiving module configured to receive a scan mode signal designating the test mode, a mask module configured to mask the secret data when the mode signal receiving module receives the scan mode signal, and an error detection module configured to detect presence or absence of error in the secret data and to store detection result in a first flip-flop.
Public/Granted literature
- US20090300371A1 SEMICONDUCTOR INTEGRATED DEVICE AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED DEVICE Public/Granted day:2009-12-03
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