Invention Grant
US08386747B2 Processor and method for dynamic and selective alteration of address translation
有权
用于动态和选择性地改变地址转换的处理器和方法
- Patent Title: Processor and method for dynamic and selective alteration of address translation
- Patent Title (中): 用于动态和选择性地改变地址转换的处理器和方法
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Application No.: US12483051Application Date: 2009-06-11
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Publication No.: US08386747B2Publication Date: 2013-02-26
- Inventor: William C. Moyer , James B. Eifert
- Applicant: William C. Moyer , James B. Eifert
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Zagorin O'Brien Graham LLP
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/28 ; G06F9/46 ; G06F9/00 ; G11C8/00

Abstract:
Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.
Public/Granted literature
- US20100318761A1 PROCESSOR AND METHOD FOR DYNAMIC AND SELECTIVE ALTERATION OF ADDRESS TRANSLATION Public/Granted day:2010-12-16
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