Invention Grant
- Patent Title: SMT/ECO mode based on cache miss rate
- Patent Title (中): 基于缓存未命中率的SMT / ECO模式
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Application No.: US13458062Application Date: 2012-04-27
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Publication No.: US08386726B2Publication Date: 2013-02-26
- Inventor: Nathan D. Fontenot , Ryan P. Grimm , Monty C. Poppe , Joel H. Schopp , Michael T. Strosaker
- Applicant: Nathan D. Fontenot , Ryan P. Grimm , Monty C. Poppe , Joel H. Schopp , Michael T. Strosaker
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Yee & Associates, P.C.
- Agent Steven L. Bennett
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A computer implemented method for managing an execution mode for a parallel processor is provided. A monitor identifies a first efficiency rate for a first contested resource of the parallel processor operating in a first operating mode. Responsive to identifying the first efficiency rate for the first contested resource, the monitor identifies whether the first efficiency rate for the contested resource of the parallel processor operating in the first operating mode exceeds a threshold. Responsive to identifying that the efficiency rate for the contested resource exceeds the threshold, an operation of the parallel processor is changed to a second operating mode.
Public/Granted literature
- US20120216030A1 SMT/ECO MODE BASED ON CACHE MISS RATE Public/Granted day:2012-08-23
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