Invention Grant
US08386716B2 Apparatus and methods to reduce castouts in a multi-level cache hierarchy
有权
减少多级缓存层次结构中的丢弃的装置和方法
- Patent Title: Apparatus and methods to reduce castouts in a multi-level cache hierarchy
- Patent Title (中): 减少多级缓存层次结构中的丢弃的装置和方法
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Application No.: US13292651Application Date: 2011-11-09
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Publication No.: US08386716B2Publication Date: 2013-02-26
- Inventor: Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
- Applicant: Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter M. Kamarchik; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
Techniques and methods are used to control allocations of cache lines to a higher level cache that have been displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby the displaced cache line castouts are not allocated to the higher level cache. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
Public/Granted literature
- US20120059995A1 Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy Public/Granted day:2012-03-08
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