In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.