Invention Grant
US08386682B2 Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform
有权
用于在多数据总线平台中维持交易同步的方法,装置和系统
- Patent Title: Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform
- Patent Title (中): 用于在多数据总线平台中维持交易同步的方法,装置和系统
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Application No.: US12827684Application Date: 2010-06-30
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Publication No.: US08386682B2Publication Date: 2013-02-26
- Inventor: Kah Meng Yeem , Mikal C. Hunsaker , Darren L. Abramson , Raul N. Gutierrez , Khee Wooi Lee
- Applicant: Kah Meng Yeem , Mikal C. Hunsaker , Darren L. Abramson , Raul N. Gutierrez , Khee Wooi Lee
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F13/36
- IPC: G06F13/36 ; G06F12/00

Abstract:
Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.
Public/Granted literature
- US20120005386A1 METHOD, APPARATUS AND SYSTEM FOR MAINTAINING TRANSACTION COHERECY IN A MULTIPLE DATA BUS PLATFORM Public/Granted day:2012-01-05
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