A bit selection circuit that arbitrarily selects, from among (2n) input bits, (2n−1) continuous output bits in the input bit arrangement (where n≧3), includes: a first multiplexer selecting {(2n−2)−(20+21+ . . . +2n−3)} continuous bits in the input bit arrangement from among (2n−2) input bits, excluding two first and (2n)th input bits at both ends in the input bit arrangement, in accordance with an input first control signal; and a second multiplexer selecting (2n−1) continuous output bits in the input bit arrangement from among the {(2n−2)−(20+21+ . . . +2n−3)} bits selected by the first multiplexer, the first input bit, and the (2n)th input bit in accordance with an input second control signal.