A frame sync detecting circuit and FSK receiver sequentially derive a moving average value (□) from oversample values of a received word pattern, for given symbol periods, and a difference between the moving average value and an average value for the given symbol periods in a given sync word pattern is determined as DC offsets Δf. Subsequently, the DC offset Δf is subtracted from the received word pattern, and correlation processing with respect to the sync word pattern is performed to determine a correlation value (●). If the correlation value exceeds a predetermined threshold, it is determined that a sync word candidate has been received, and symbol values of the received word pattern after the DC offset correction are compared with respective symbol values of the sync word pattern. A sync word pattern detection is determined if errors in the symbols are within a given range.