Invention Grant
US08385398B2 Receiver with chip-level equalisation 有权
接收机具有芯片级均衡

Receiver with chip-level equalisation
Abstract:
The present invention relates to receiver apparatuses and methods of controlling weight adaptation in a receiver of a code multiplex telecommunications system with orthogonal spreading codes, wherein received discrete time signal samples are chip-level filtered by using a first equalizing step. Additionally, the received discrete time signal samples are delayed by a time period corresponding to a data symbol and used in a second equalizing step. Symbol estimates obtained from the first equalizing step are non-linearly filtered and used as a desired response for the second equalizing step in the following symbol period, wherein equalizer weights adapted in the second equalizing step are used for the first equalizing step. Alternatively, the second equalizing step may be dispensed with and weight adaptation may be incorporated in a single equalizing step. As an additional or alternative option, a hybrid equalizer architecture may be provided, where the above two-step equalization is used during an active phase where a channel is allocated, while another weight updating scheme is used during an inactive phase where no channel is assigned. Thereby, detrimental effects of interference power can be reduced at low increase in complexity.
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