A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies elementary operations for each stage except an initial stage of the programmable compute pipeline. The programmable compute pipeline includes a sequence of stages beginning with the initial stage. The initial stage includes an operation selector that selects the respective set for the type of each packet. Each stage except the initial stage includes elementary components that are programmable to concurrently perform each of multiple combinations of elementary operations. The elementary components concurrently perform a selected one of the combinations for each packet. The selected combination includes the elementary operations specified for the stage in the respective set that the operation selector selects for the packet's type.