Invention Grant
- Patent Title: Semiconductor memory device and decoding method
- Patent Title (中): 半导体存储器件及解码方法
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Application No.: US13233530Application Date: 2011-09-15
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Publication No.: US08385117B2Publication Date: 2013-02-26
- Inventor: Kenji Sakurada , Hironori Uchikawa
- Applicant: Kenji Sakurada , Hironori Uchikawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-045477 20110302
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio.
Public/Granted literature
- US20120224420A1 SEMICONDUCTOR MEMORY DEVICE AND DECODING METHOD Public/Granted day:2012-09-06
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