A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.