Invention Grant
- Patent Title: Soft-error resistant latch
- Patent Title (中): 防软锁存器
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Application No.: US12960548Application Date: 2010-12-06
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Publication No.: US08384419B2Publication Date: 2013-02-26
- Inventor: Kevin P. Lavery , Jason P. Whiles
- Applicant: Kevin P. Lavery , Jason P. Whiles
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H03K19/003
- IPC: H03K19/003

Abstract:
A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types.
Public/Granted literature
- US20120139578A1 SOFT-ERROR RESISTANT LATCH Public/Granted day:2012-06-07
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