Invention Grant
- Patent Title: Wafer level molding structure
- Patent Title (中): 晶圆级成型结构
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Application No.: US12981475Application Date: 2010-12-30
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Publication No.: US08384215B2Publication Date: 2013-02-26
- Inventor: Su-Tsai Lu , Jing-Ye Juang , Yu-Min Lin
- Applicant: Su-Tsai Lu , Jing-Ye Juang , Yu-Min Lin
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW99146766A 20101230
- Main IPC: H01L23/485
- IPC: H01L23/485 ; H01L23/496

Abstract:
A wafer level molding structure including a first chip, a second chip and an adhesive layer therebetween is provided. The first chip includes a first back side, a first front side and a plurality of lateral sides, and a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through electrodes are disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials including a plurality of conductive particles cover the lateral sides, and electrically connect the second back side bumps with the first front side bumps.
Public/Granted literature
- US20120168933A1 WAFER LEVEL MOLDING STRUCTURE Public/Granted day:2012-07-05
Information query
IPC分类: