Invention Grant
- Patent Title: System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
- Patent Title (中): 执行下一个布置和修剪不允许的布局以编程集成电路的系统和方法
-
Application No.: US12132527Application Date: 2008-06-03
-
Publication No.: US08370791B2Publication Date: 2013-02-05
- Inventor: Kenneth Y. Ogami , Frederick R. Hood
- Applicant: Kenneth Y. Ogami , Frederick R. Hood
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a data driven model for matching the hardware resource requirements for an associated user module and the available hardware resources on an underlying chip. Databases are utilized to describe the hardware resource requirements which are dictated by the particular user module and the available hardware resources of a particular chip. The user module descriptive database can be updated in response to additional user modules being added or changes to the hardware resource requirements of existing user modules. The hardware description database can be updated in response to additional chips being added. Further, the graphical interface relates both a user module and the possible hardware resource. This graphical interface utilizes highlights of both the module and the associated resource in patterns, grayscales, or colors to graphically illustrate the relationship between the module and the associated resource.
Public/Granted literature
Information query