Invention Grant
- Patent Title: Multiple-level memory cells and error detection
- Patent Title (中): 多级存储单元和错误检测
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Application No.: US12425139Application Date: 2009-04-16
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Publication No.: US08370709B2Publication Date: 2013-02-05
- Inventor: Kurt Ware
- Applicant: Kurt Ware
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed.
Public/Granted literature
- US20100269016A1 MULTIPLE-LEVEL MEMORY CELLS AND ERROR DETECTION Public/Granted day:2010-10-21
Information query
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