Invention Grant
- Patent Title: Semiconductor memory device including charge accumulation layer
- Patent Title (中): 半导体存储器件包括电荷累积层
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Application No.: US12817665Application Date: 2010-06-17
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Publication No.: US08369152B2Publication Date: 2013-02-05
- Inventor: Takeshi Shimane , Naoyuki Shigyo , Mutsuo Morikado
- Applicant: Takeshi Shimane , Naoyuki Shigyo , Mutsuo Morikado
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2009-145471 20090618; JP2010-098188 20100421
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04 ; G11C16/06

Abstract:
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.
Public/Granted literature
- US20100322009A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING CHARGE ACCUMULATION LAYER Public/Granted day:2010-12-23
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