A semiconductor memory device measures a leakage current generated when a unit cell is accessed during a test process. The semiconductor memory device includes a unit cell configured to include a memory element, a word line configured to be coupled to one end of the unit cell, and a bit line configured to be coupled to the other end of the unit cell. In a normal operation, a current signal flows from the bit line to the word line through the unit cell such that data stored in the memory element is read. In a test operation, the word line is deactivated and a read operation is carried out such that data stored in the memory element is read.