Invention Grant
- Patent Title: Delay locked loop
- Patent Title (中): 延迟锁定环路
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Application No.: US13190841Application Date: 2011-07-26
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Publication No.: US08368446B2Publication Date: 2013-02-05
- Inventor: Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
- Applicant: Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2011-0037203 20110421
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.
Public/Granted literature
- US20120268180A1 DELAY LOCKED LOOP Public/Granted day:2012-10-25
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