During an asymmetry testing mode of an integrated circuit, the asymmetry of an on-chip I/O circuit is tested. In particular, a transmitter circuit in the integrated circuit transmits electrical signals, which are associated with a predefined data pattern, to a receiver circuit in the integrated circuit via a communication channel (such as a differential pair of signal lines). Then the integrated circuit generates an eye pattern using the received electrical signals, and determines an asymmetry of the eye pattern about a common reference level of the received electrical signals. Furthermore, the integrated circuit performs remedial action based on the determined asymmetry. For example, the integrated circuit may compare the determined asymmetry with a predefined asymmetry criterion and, if the asymmetry exceeds the predefined asymmetry criterion, may output a result of the comparison that indicates a failure of the asymmetry test.