Invention Grant
US08368225B2 Semiconductor integrated circuit device having improved interconnect accuracy near cell boundaries
有权
半导体集成电路器件在电池边界附近具有改进的互连精度
- Patent Title: Semiconductor integrated circuit device having improved interconnect accuracy near cell boundaries
- Patent Title (中): 半导体集成电路器件在电池边界附近具有改进的互连精度
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Application No.: US13113644Application Date: 2011-05-23
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Publication No.: US08368225B2Publication Date: 2013-02-05
- Inventor: Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
- Applicant: Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-176143 20080704
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L27/04
Abstract:
A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
Public/Granted literature
- US20110221067A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2011-09-15
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