Invention Grant
- Patent Title: Dual bit line metal layers for non-volatile memory
- Patent Title (中): 用于非易失性存储器的双位线金属层
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Application No.: US11768468Application Date: 2007-06-26
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Publication No.: US08368137B2Publication Date: 2013-02-05
- Inventor: Nima Mokhlesi , Jun Wan
- Applicant: Nima Mokhlesi , Jun Wan
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies Inc.
- Current Assignee: SanDisk Technologies Inc.
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus & DeNiro LLP
- Main IPC: H01L29/788
- IPC: H01L29/788

Abstract:
Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4ƒpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.
Public/Granted literature
- US20090003025A1 DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY Public/Granted day:2009-01-01
Information query
IPC分类: