Invention Grant
- Patent Title: Three-dimensional integrated circuit structure
- Patent Title (中): 三维集成电路结构
-
Application No.: US12881961Application Date: 2010-09-14
-
Publication No.: US08367524B2Publication Date: 2013-02-05
- Inventor: Sang-Yun Lee
- Applicant: Sang-Yun Lee
- Agent Greg L. Martinez
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/331

Abstract:
A method of forming a semiconductor structure includes coupling a semiconductor structure to an interconnect region through a bonding region. The interconnect region includes a conductive line in communication with the bonding region. The bonding region includes a metal layer which covers the interconnect region. The semiconductor structure is processed to form a vertically oriented semiconductor device.
Public/Granted literature
- US20110003438A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE Public/Granted day:2011-01-06
Information query
IPC分类: