Invention Grant
- Patent Title: Manufacturing method for high voltage transistor
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Application No.: US13041752Application Date: 2011-03-07
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Publication No.: US08367511B2Publication Date: 2013-02-05
- Inventor: Yu-Hsien Chin , Chih-Chia Hsu , Yin-Fu Huang
- Applicant: Yu-Hsien Chin , Chih-Chia Hsu , Yin-Fu Huang
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack LLP
- Main IPC: H01L21/331
- IPC: H01L21/331

Abstract:
A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.
Public/Granted literature
- US20120231597A1 Manufacturing Method for High Voltage Transistor Public/Granted day:2012-09-13
Information query
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