Invention Grant
- Patent Title: Oxide terminated trench MOSFET with three or four masks
- Patent Title (中): 具有三个或四个掩模的氧化物端接沟槽MOSFET
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Application No.: US12731112Application Date: 2010-03-24
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Publication No.: US08367501B2Publication Date: 2013-02-05
- Inventor: Sik Lui , Anup Bhalla
- Applicant: Sik Lui , Anup Bhalla
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: JDI PATENT
- Agent Joshua D. Isenberg
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/105
Abstract:
An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.
Public/Granted literature
- US20110233666A1 OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS Public/Granted day:2011-09-29
Information query
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