Invention Grant
US08367474B2 Method of manufacturing integrated circuit having stress tuning layer
有权
具有应力调谐层的集成电路的制造方法
- Patent Title: Method of manufacturing integrated circuit having stress tuning layer
- Patent Title (中): 具有应力调谐层的集成电路的制造方法
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Application No.: US12983967Application Date: 2011-01-04
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Publication No.: US08367474B2Publication Date: 2013-02-05
- Inventor: Shin-Puu Jeng , Clinton Chao , Szu Wei Lu
- Applicant: Shin-Puu Jeng , Clinton Chao , Szu Wei Lu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
Public/Granted literature
- US20110097893A1 Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same Public/Granted day:2011-04-28
Information query
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