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US08352819B2 State retention using a variable retention voltage 有权
使用可变保持电压保持状态

State retention using a variable retention voltage
Abstract:
A data processing apparatus is provided with state retention circuits into which state values are saved from nodes within the data processing circuitry when entering a sleep mode from an active mode. Error management circuitry is coupled to the state retention circuits and detects errors in the retention of the state values. If errors are detected then an error recover response is triggered. A voltage controller coupled to the error management circuitry serves to vary a supply voltage to the state retention circuits during the sleep mode so as to maintain a finite non-zero error rate in the retention of the state values by the state retention circuits.
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