Invention Grant
- Patent Title: Bitline floating circuit for memory power reduction
- Patent Title (中): 位线浮动电路用于存储器功率降低
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Application No.: US12976412Application Date: 2010-12-22
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Publication No.: US08351287B1Publication Date: 2013-01-08
- Inventor: Rohith Sood , Fabiano Fontana , Zheng Chen
- Applicant: Rohith Sood , Fabiano Fontana , Zheng Chen
- Applicant Address: US OR Hillsboro
- Assignee: Lattice Semiconductor Corporation
- Current Assignee: Lattice Semiconductor Corporation
- Current Assignee Address: US OR Hillsboro
- Agency: Haynes and Boone, LLP
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.
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