A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers (2) and the second conductive layers (14). The method includes: forming a first interlayer insulating film (3); forming a contact hole in the interlayer insulating film (3); depositing a first plug material (4) in the contact hole and on the first interlayer insulating film (3); performing a first polishing in which the first plug material (4) is polished until the first interlayer insulating film (3) is exposed; depositing a conductive film (6a) that becomes a first electrode (6) of the current steering element (10), on the first plug material (4) and the first interlayer insulating film (3) after the first polishing; and performing a second polishing in which a surface of the conductive film (6a) is polished.