Invention Grant
- Patent Title: Accelerating model checking via synchrony
- Patent Title (中): 通过同步加速模型检查
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Application No.: US12054575Application Date: 2008-03-25
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Publication No.: US08286137B2Publication Date: 2012-10-09
- Inventor: Vineet Kahlon , Aarti Gupta
- Applicant: Vineet Kahlon , Aarti Gupta
- Applicant Address: US NJ Princeton
- Assignee: NEC Laboratories America, Inc.
- Current Assignee: NEC Laboratories America, Inc.
- Current Assignee Address: US NJ Princeton
- Agent Joseph Kolodka; James Bitetto
- Main IPC: G06F9/44
- IPC: G06F9/44

Abstract:
A system and method for program verification by model checking in concurrent programs includes modeling each of a plurality of program threads as a circuit model, and generating a full circuit for an entire program by combining the circuit models including constraints which enforce synchronous execution of the program threads. The program is verified using the synchronous execution to reduce an amount of memory needed to verify the program and a number of steps taken to uncover an error.
Public/Granted literature
- US20080282221A1 ACCELERATING MODEL CHECKING VIA SYNCHRONY Public/Granted day:2008-11-13
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