Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.