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US08284614B2 Refresh control circuit and method for semiconductor memory device 失效
用于半导体存储器件的刷新控制电路和方法

Refresh control circuit and method for semiconductor memory device
Abstract:
A semiconductor memory device includes a refresh counter for counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode, an external address input buffer for buffering an external address to output an internal address in response to a mode selection signal enabled in an external address refresh mode, an address selector for outputting the refresh address from the refresh counter as a selection row address in a normal refresh mode and outputting the internal address from the external address input buffer as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal, and a row address decoder for generating a row address selection signal for sequentially accessing word lines by decoding the selection row address.
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