Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.