A flat panel display is disclosed. The flat panel display includes a display panel including data lines, gate lines crossing the data lines, pixels arranged in a matrix format, and a pixel array that allows images to be simultaneously displayed on one screen by suitably disposing the images on one screen, a data drive circuit supplying data to the data lines, a gate drive circuit supplying scan signals to the gate lines, a scalar board converting a resolution of each of the images, and a control board that supplies data received from the scalar board to the data drive circuit and controls operation timing of the data drive circuit and operation timing of the gate drive circuit. a ratio of a horizontal length to a vertical length of the pixel array is 21.3-26.7:10.