Invention Grant
- Patent Title: Voltage reducing circuit
- Patent Title (中): 降压电路
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Application No.: US12839033Application Date: 2010-07-19
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Publication No.: US08258859B2Publication Date: 2012-09-04
- Inventor: Toshikatsu Jinbo
- Applicant: Toshikatsu Jinbo
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2009-197541 20090828
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.
Public/Granted literature
- US20110050186A1 VOLTAGE REDUCING CIRCUIT Public/Granted day:2011-03-03
Information query
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