Invention Grant
US08258029B2 Semiconductor structure and process for reducing the second bit effect of a memory device
有权
用于降低存储器件的第二位效应的半导体结构和工艺
- Patent Title: Semiconductor structure and process for reducing the second bit effect of a memory device
- Patent Title (中): 用于降低存储器件的第二位效应的半导体结构和工艺
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Application No.: US11786078Application Date: 2007-04-10
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Publication No.: US08258029B2Publication Date: 2012-09-04
- Inventor: Chao-I Wu , Tzu-Hsuan Hsu
- Applicant: Chao-I Wu , Tzu-Hsuan Hsu
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Main IPC: H01L31/113
- IPC: H01L31/113 ; H01L21/336

Abstract:
A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened.
Public/Granted literature
- US20080251831A1 Semiconductor structure and process for reducing the second bit effect of a memory device Public/Granted day:2008-10-16
Information query
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