Invention Grant
US08258016B2 Semiconductor package having increased resistance to electrostatic discharge
有权
具有增加的对静电放电的抗性的半导体封装
- Patent Title: Semiconductor package having increased resistance to electrostatic discharge
- Patent Title (中): 具有增加的对静电放电的抗性的半导体封装
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Application No.: US12337519Application Date: 2008-12-17
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Publication No.: US08258016B2Publication Date: 2012-09-04
- Inventor: Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
- Applicant: Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Beyer Law Group LLP
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.
Public/Granted literature
- US20090104735A1 SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE Public/Granted day:2009-04-23
Information query
IPC分类:
