Invention Grant
US08239803B2 Layout method and layout apparatus for semiconductor integrated circuit
失效
半导体集成电路的布局方法和布局装置
- Patent Title: Layout method and layout apparatus for semiconductor integrated circuit
- Patent Title (中): 半导体集成电路的布局方法和布局装置
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Application No.: US13137201Application Date: 2011-07-27
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Publication No.: US08239803B2Publication Date: 2012-08-07
- Inventor: Naohiro Kobayashi
- Applicant: Naohiro Kobayashi
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-233285 20070907
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A layout method of a semiconductor integrated circuit by using cell library data includes specifying a gate in a predetermined cell as a reference gate, and automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from the reference gate meets a preset gate data density condition.
Public/Granted literature
- US20110289467A1 Layout method and layout apparatus for semiconductor integrated circuit Public/Granted day:2011-11-24
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