A timing analyzing system includes an RC extracting section configured to generate an SPEF (Standard Parasitic Exchange Format) file which contains resistance and capacitance components of wirings; a delay calculating section configured to generate an SDF (Standard Delay Format) file based on the SPEF file; and a clock mesh calculating section configured to generate a corrected circuit model by simplifying a netlist on a clock path to pass through a clock mesh structure from an input stage. A timing analysis section is configured to perform timing analysis of a semiconductor integrated circuit of an analysis target based on the corrected circuit model.