Invention Grant
US08239439B2 Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor 失效
在向量微处理器中实现最小面积消耗多重加法浮点求和函数的方法和装置

Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor
Abstract:
Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises transferring more than two operands to a vector unit, each operand being transferred to a respective one of a plurality of processing lanes of the vector unit. The operands may be transferred from the vector unit to a dot product unit wherein an arithmetic operation using the more than two operands may be performed.
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