Invention Grant
- Patent Title: Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor
- Patent Title (中): 在向量微处理器中实现最小面积消耗多重加法浮点求和函数的方法和装置
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Application No.: US11955679Application Date: 2007-12-13
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Publication No.: US08239439B2Publication Date: 2012-08-07
- Inventor: Adam J. Muff , Matthew R. Tubbs
- Applicant: Adam J. Muff , Matthew R. Tubbs
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson & Sheridan LLP
- Main IPC: G06F7/38
- IPC: G06F7/38

Abstract:
Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises transferring more than two operands to a vector unit, each operand being transferred to a respective one of a plurality of processing lanes of the vector unit. The operands may be transferred from the vector unit to a dot product unit wherein an arithmetic operation using the more than two operands may be performed.
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