A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.