Invention Grant
- Patent Title: Voltage regulator with high noise rejection
- Patent Title (中): 具有高噪声抑制功能的稳压器
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Application No.: US12760643Application Date: 2010-04-15
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Publication No.: US08237425B1Publication Date: 2012-08-07
- Inventor: Mian Z. Smith , Joseph Michael Ingino
- Applicant: Mian Z. Smith , Joseph Michael Ingino
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ward & Zinna, LLC
- Main IPC: G05F3/16
- IPC: G05F3/16 ; G05F1/40

Abstract:
To improve noise rejection, a native (or undoped) NMOS transistor is used as a source follower in place of a conventional common source PMOS transistor in a voltage regulator circuit. The native transistor has a threshold voltage of approximately 0 volts which allows the maximum voltage output of the regulator to be higher by one threshold voltage of a conventional NMOS transistor than might be obtained from a voltage regulator that used a conventional NMOS transistor. Alternatively, a depletion transistor can be used to provide even higher output. In another illustrative embodiment, a conventional bandgap reference circuit is modified by replacing a common source transistor connected to the output of an op amp with a native MOS transistor connected as a source follower.
Information query
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