Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US12874719Application Date: 2010-09-02
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Publication No.: US08237280B2Publication Date: 2012-08-07
- Inventor: Akio Kiyota
- Applicant: Akio Kiyota
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2007-276325 20071024; JP2008-000339 20080107
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
The present invention proposes a dummy metal fill structure which makes it possible to reduce variations in transistor characteristics as much as possible even if mask misalignment occurs, as well as to ensure the intended planarizing effect of the metal CMP process. The dummy metal fill formed above the gate electrode extends in the gate length direction with both ends thereof protruding from a region corresponding to the gate electrode. Even if a mask for forming a wiring layer is misaligned and the position of the dummy metal fill is misaligned from an intended position, the shape of the dummy metal fill within a region of the gate electrode is kept symmetric with respect to the center of the gate electrode.
Public/Granted literature
- US20100327331A1 SEMICONDUCTOR DEVICE Public/Granted day:2010-12-30
Information query
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