Invention Grant
US08236708B2 Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor
失效
使用双(二乙基氨基)硅烷(C 8 H 22 N 2 Si)作为硅前体的减少图案负载
- Patent Title: Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor
- Patent Title (中): 使用双(二乙基氨基)硅烷(C 8 H 22 N 2 Si)作为硅前体的减少图案负载
-
Application No.: US12855877Application Date: 2010-08-13
-
Publication No.: US08236708B2Publication Date: 2012-08-07
- Inventor: Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
- Applicant: Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/316
- IPC: H01L21/316 ; C23C16/40

Abstract:
Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
Public/Granted literature
- US20110223774A1 REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR Public/Granted day:2011-09-15
Information query
IPC分类: