Invention Grant
- Patent Title: Manufacturing method of semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
-
Application No.: US12716928Application Date: 2010-03-03
-
Publication No.: US08236681B2Publication Date: 2012-08-07
- Inventor: Makoto Nagano
- Applicant: Makoto Nagano
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Womble Carlyle
- Priority: JP2009-051668 20090305
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value. According to the invention, in a via hole formation step in a damascene semi-global interconnect or the like, dry etching treatment of a via-bottom etch stop film is performed and then, after nitrogen plasma treatment in the same treatment chamber, electrostatic charge removal treatment by using argon plasma is performed.
Public/Granted literature
- US20100227470A1 Manufacturing Method of Semiconductor Integrated Circuit Device Public/Granted day:2010-09-09
Information query
IPC分类: