Invention Grant
- Patent Title: Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner
- Patent Title (中): 浅沟槽隔离用于结合侧墙和底衬的SOI结构
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Application No.: US11788184Application Date: 2007-04-18
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Publication No.: US08236638B2Publication Date: 2012-08-07
- Inventor: Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
- Applicant: Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/336 ; H01L21/76
Abstract:
A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
Public/Granted literature
- US20080261361A1 Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner Public/Granted day:2008-10-23
Information query
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