Invention Grant
- Patent Title: Packaging an integrated circuit die with backside metallization
- Patent Title (中): 封装具有背面金属化的集成电路管芯
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Application No.: US12184377Application Date: 2008-08-01
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Publication No.: US08236609B2Publication Date: 2012-08-07
- Inventor: Lakshmi N. Ramanathan , Craig S. Amrine , Jianwen Xu
- Applicant: Lakshmi N. Ramanathan , Craig S. Amrine , Jianwen Xu
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Meschkow & Gresham, P.L.C.
- Main IPC: H01L21/56
- IPC: H01L21/56
Abstract:
A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).
Public/Granted literature
- US20100029045A1 PACKAGING AN INTEGRATED CIRCUIT DIE WITH BACKSIDE METALLIZATION Public/Granted day:2010-02-04
Information query
IPC分类:
