Invention Grant
- Patent Title: Incremental placement and routing
- Patent Title (中): 增量放置和布线
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Application No.: US12751175Application Date: 2010-03-31
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Publication No.: US08196081B1Publication Date: 2012-06-05
- Inventor: Hasan Arslan , Vinay Verma , Sandor Kalman
- Applicant: Hasan Arslan , Vinay Verma , Sandor Kalman
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent LeRoy D. Maunu; Lois D. Cartier
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.
Information query