A process is provided for creating an input/output (I/O) model. A set of logical I/O pins of an unplaced and unrouted circuit design is determined. Pin placement is determined for one or more of the logical I/O pins on device pins of a target device. An I/O pin profile for each of the logical I/O pins is determined. A plurality of I/O pin models available on the target device are input and an I/O pin model is selected from the plurality of I/O pin models for each of the logical I/O pins according to the respective I/O pin profiles. An I/O model is generated including each selected I/O pin model within the I/O model. The generated I/O model is stored in a processor readable storage medium.