Invention Grant
- Patent Title: Hybrid transactions for low-overhead speculative parallelization
- Patent Title (中): 低架构投机并行化的混合交易
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Application No.: US11965120Application Date: 2007-12-27
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Publication No.: US08195898B2Publication Date: 2012-06-05
- Inventor: Adam Welc , Ali-Reza Adl-Tabatabai
- Applicant: Adam Welc , Ali-Reza Adl-Tabatabai
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F13/14
- IPC: G06F13/14

Abstract:
A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially.
Public/Granted literature
- US20090172303A1 HYBRID TRANSACTIONS FOR LOW-OVERHEAD SPECULATIVE PARALLELIZATION Public/Granted day:2009-07-02
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